1. Field of the Invention
The present invention relates generally to a voltage controlled oscillation circuit and, more particularly, to a voltage controlled oscillation circuit used in a phase locked loop circuit constructed as an integrated circuit.
2. Description of the Related Art
A voltage controlled oscillation circuit is generally constructed by using a Phase-Locked Loop (PLL) circuit. The phase-locked circuit (PLL) is, as illustrated in a block diagram of FIG. 1, constructed, as a feedback circuit, of a phase frequency comparing circuit (PFC) 10, a charge pump circuit (CP) 20, a low-pass filter (LPF) 30, a voltage controlled oscillation circuit (Vco) 40 and a frequency dividing circuit (divider) 50. Further, the voltage controlled oscillation circuit (Vco) 40 is, as shown in FIG. 2, constructed of a voltage controlled current generating circuit (CG) 60 and a current controlled oscillation circuit (Cco) 70.
The phase frequency comparing circuit (PFC) 10 receives as inputs both a reference signal (Fref) generated externally and an output signal (Fout/N) of the frequency dividing circuit (divider) 50. PFC 10 compares phases and frequencies of Fref and Fout/N, and generates control signals (UP and DOWN) having magnitudes in such a direction as to reduce differences therebetween. The charge pump circuit (CP) 20 receives input signals (UP and DOWN) from PFC 10, and charges and discharges a control voltage (Vcnt) through LPF 30. LPF 30 effects DC averaging of potential changes in the control voltage (Vcnt) due to charging/discharging currents from the charge pump circuit (CP) 20. The voltage controlled current generating circuit (CG) 60 generates a bias current (Ibias) proportional to input signal Vcnt, and the current controlled oscillation circuit (Cco) 70 outputs an oscillation signal Fout proportional to the bias current (Ibias). The frequency dividing circuit (divider) 50 receives oscillation signal Fout, and generates signal Fout/N, the frequency of which is the frequency of Fout divided by N.
The PLL circuit constructed above compares the frequency and/or phase of the reference signal Fref with the frequency and/or phase of the signal Fout/N, the frequency of which is the frequency of the oscillation output signal Fout of the voltage control oscillation circuit (Vco) is divided by N. The PLL circuit utilizes a feedback loop to reduce differences between the respective frequencies and phases of Fref and Fout/N, thereby obtaining an oscillation output signal Fout synchronized in frequency and phase with the reference signal Fref.
Electrical characteristics such as the voltage-current characteristic and threshold of a transistor constituting the integrated voltage controlled oscillation circuit (Vco) 40, largely change depending upon variations in manufacturing conditions. Corresponding to this, the input control voltage (Vcnt)-oscillation signal Fout characteristic of the voltage control oscillation circuit (Vco) 40 also changes. Even if there is variation in the manufacturing conditions, the output signal Fout of the voltage controlled oscillation circuit (Vco) 40 is synchronized with a desired frequency. It is common to design extra gain into the control voltage (Vcnt)-oscillation Fout characteristic so as to obtain the desired Fout oscillation frequency corresponding to the available control voltage Vcnt range regardless of variation.
On the other hand, even if a minute amount of noise enters the input voltage (Vcnt) of the voltage controlled oscillation circuit (Vco) 40, the frequency of the oscillation output signal Fout fluctuates in proportion to fluctuations in the input voltage (Vcnt), and jitter occurs. The magnitude of this jitter is proportional to the gain of the input voltage (Vcnt)-oscillation signal (fout) frequency characteristic of the voltage controlled oscillation circuit (Vco) 40. Accordingly, the voltage controlled oscillation circuit (Vco) 40 exhibiting a low gain is required for attaining the phase-locked loop circuit (PLL) having a low jitter characteristic. Further, it is of importance for designing the phase-locked loop circuit (PLL) to obtain the ensured synchronizing operation and a low jitter characteristic.
FIG. 3 shows a circuit construction proposed in Japanese Patent Application Laid-Open No. Hei 2-311009 as an example of the voltage controlled oscillation circuit (Vco) 40 which hitherto has been used in the phase-locked loop circuit (PLL).
The voltage controlled oscillation circuit (Vco) shown in FIG. 3 uses separate first and second voltage controlled current generating circuits (Ibias1, Ibias2) 102, 103 for forming the control voltage (Vcnt). The gain of the control voltage (Vcnt)-oscillation frequency (fout) characteristic of the voltage controlled oscillation circuit (Vco) when using the second voltage controlled current source (Ibias2) is lower than when using the first voltage control current source (Ibias1) 102.
Provided further are a current adjusting circuit 80 for adjusting the characteristic of the second voltage controlled current source (Ibias2) 103 in order to equalize the bias currents (Ibias1, Ibias2) of the first and second voltage controlled current sources 102, 103, and an external control signal (a switch 90) for switching the driving current source of the oscillation circuit with the first voltage controlled current source (Ibias1) 102 and the second voltage control current source (Ibias2) 103. The current adjusting circuit 80 includes a circuit for making a comparison between the current values of the first and second voltage controlled current sources (Ibias1, Ibias2) 102, 103, and a counter circuit for receiving a result of this comparison and adjusting the current value of the second voltage controlled current source (Ibias2) 103 by addition and subtraction.
When starting the phase-locked operation of the phase-locked loop circuit (PLL), the phase/frequency synchronization is effected by use of the first voltage controlled current source (Ibias1) 102 having a large gain of the control voltage (Vcnt)-oscillation output signal (fout) characteristic. Simultaneously with this, the current adjusting circuit 80 adjusts the current by increasing and decreasing a value of a counter circuit so that the value of the bias current (Ibias2) of the second voltage controlled current source 103 is equalized to the value of the bias current (Ibias1) of the first voltage controlled current source 102. After achieving synchronism of the frequency and/or phase of the phase-locked loop circuit (PLL), the operation of the counter circuit is stopped by the external control signal (the switch 90), and the counter circuit value is set to a fixed state. The characteristic of the control voltage (Vcnt)-oscillation output signal (fout) in this state becomes as shown in FIG. 4, with operating point C.
Next, in this state, the current source is switched by the external control signal (the switch 90) from the first voltage controlled current source (Ibias1) 102 to the second voltage controlled current source (Ibias2) having the low current gain. The input voltage (Vcnt)-oscillation frequency (fout) characteristic of the voltage controlled oscillation circuit (Vco) is changed from characteristic A to characteristic B in FIG. 4 while maintaining the operating point of the phase-locked loop circuit (PLL).
When starting the phase-locked operation of the phase-locked loop circuit (PLL), a frequency bandwidth of the oscillation output signal is increased by using the first voltage controlled current source (Ibias1) 102 having a large gain, and, even if there is a deviation in the oscillation frequency due to the variation in the manufacturing conditions, the operation can be surely performed at a desired frequency.
Moreover, after an end of the phase-locked operation of the PLL circuit, the current source is switched to the second voltage controlled current source (Ibias2) 103, thereby decreasing the gain of the control voltage (Vcnt)-oscillation signal output (Fout) characteristic and also decreasing the jitter characteristic.
However, the voltage control oscillation circuit Vco of prior art phase-locked loop circuit (PLL) described above, because of switching in the input voltage (Vcnt)-oscillation frequency (fout) characteristic, requires the external control signal terminal and the circuit for determining phase-locked operation, and further the current adjusting circuit 80 for the first current source (Ibias1) and the second current source (Ibias2), which leads to problems such as an increase in the number of input terminals and an increase in circuit size.